MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 366

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.2.4.14 Descriptor Individual Upper Address Register (IAUR)
The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit individual
address hash table used in the address recognition process to check for possible match with the DA
field of receive frames with an individual DA. This register is not reset and must be initialized by
the user.
19.2.4.15 Descriptor Individual Lower Address Register (IALR)
The IALR register is written by the user. This register contains the lower 32 bits of the 64-bit
individual address hash table used in the address recognition process to check for possible match
with the DA field of receive frames with an individual DA. This register is not reset and must be
initialized by the user.
19-22
Address
Reset
Reset
31–16
15–0
31–0
Bits
Bits
W
W
R
R
Figure 19-15. Descriptor Individual Upper Address Register (IAUR)
—
—
31
15
PAUSE_DUR Pause Duration field used in PAUSE frames.
IADDR1
OPCODE
Name
Name
—
—
30
14
—
—
29
13
The upper 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0
of IADDR1 contains hash index bit 32.
Opcode field used in PAUSE frames.
These bits are a constant, 0x0001.
—
—
28
12
Table 19-18. IAUR Field Descriptions
Table 19-17. OPD Field Descriptions
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—
27
11
MCF5271 Reference Manual, Rev. 2
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—
26
10
25
—
—
9
IPSBAR + 0x1118
—
—
24
IADDR1
IADDR1
8
Descriptions
23
—
—
7
Description
—
—
22
6
—
—
21
5
—
—
20
4
—
—
19
3
Freescale Semiconductor
—
—
18
2
—
—
17
1
16
—
—
0