MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 372

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.2.4.23 Receive Buffer Size Register (EMRBR)
The EMRBR is a 9-bit register programmed by the user. The EMRBR register dictates the
maximum size of all receive buffers. Note that because receive frames will be truncated at 2k-1
bytes, only bits 10–4 are used. This value should take into consideration that the receive CRC is
always written into the last receive buffer. To allow one maximum size frame per buffer, EMRBR
must be set to RCR[MAX_FL] or larger. The EMRBR must be evenly divisible by 16. To insure
this, bits 3-0 are forced low. To minimize bus utilization (descriptor fetches) it is recommended
that EMRBR be greater than or equal to 256 bytes.
The EMRBR register does not reset, and must be initialized by the user.
19.2.5 Buffer Descriptors
This section provides a description of the operation of the driver/DMA via the buffer descriptors.
It is followed by a detailed description of the receive and transmit descriptor fields.
19-28
Address
Reset
Reset
30–11
31–2
10–4
Bits
Bits
1–0
3–0
W
W
R
R
—
—
31
15
0
0
X_DES_
R_BUF_
START
Name
Name
SIZE
—
—
30
14
0
0
—
—
—
Figure 19-24. Receive Buffer Size Register (EMRBR)
—
—
29
13
0
0
Pointer to start of transmit buffer descriptor queue.
Reserved, should be cleared.
Reserved, should be written to 0 by the host processor.
Receive buffer size.
Reserved, should be written to 0 by the host processor.
Table 19-27. EMRBR Field Descriptions
Table 19-26. ETDSR Field Descriptions
—
—
28
12
0
0
—
—
27
11
0
0
MCF5271 Reference Manual, Rev. 2
—
—
26
10
0
25
—
—
0
9
IPSBAR + 0x1188
—
—
24
0
8
R_BUF_SIZE
Descriptions
Descriptions
23
—
—
0
7
—
—
22
0
6
—
—
21
0
5
—
—
20
0
4
—
—
19
0
0
3
Freescale Semiconductor
—
—
18
0
0
2
—
—
17
0
0
1
16
—
—
0
0
0