MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 107

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

EMAC_state_restore:
By executing this type of sequence, the exact state of the EMAC programming model can be
correctly saved and restored.
4.4.1.1.3
MULS and MULU are unaffected by fractional mode operation; operands are still assumed to be
integers.
4.4.1.1.4
The scale factor is ignored while the MAC is in fractional mode.
4.4.2
The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications
involved with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits
of the source operand are actually loaded into the register. When it is stored, the upper 16 bits are
all forced to ones.
This register performs a simple AND with the operand address for MAC instructions. That is, the
processor calculates the normal operand address and, if enabled, that address is then ANDed with
{0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the
operand address can be constrained to a certain memory region. This is used primarily to
implement circular queues in conjunction with the (An)+ addressing mode.
This feature minimizes the addressing support required for filtering, convolution, or any routine
that implements a data array as a circular queue. For MAC + MOVE operations, the MASK
contents can optionally be included in all memory effective address calculations. The syntax is as
follows:
MAC.sz
The & operator enables the use of MASK and causes bit 5 of the extension word to be set. The
exact algorithm for the use of MASK is as follows:
Freescale Semiconductor
movem.l (a7),#0x00ff
move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.l
Ry,RxSF,<ea>y&,Rw
Mask Register (MASK)
MULS/MULU
Scale Factor in MAC or MSAC Instructions
#0,macsr
d0,acc0
d1,acc1
d2,acc2
d3,acc3
d4,accext01
d5,accext23
d6,mask
d7,macsr
MCF5271 Reference Manual, Rev. 2
; restore the state from memory
; disable rounding in the macsr
; restore the accumulators
; restore the accumulator extensions
; restore the address mask
; restore the macsr
Memory Map/Register Definition
4-11