MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 29

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
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chapter describes the programming model and signal timing, as well as the command set
required for synchronous operations.
Chapter 19, “Fast Ethernet Controller
block diagram, and transceiver connection information for both MII (Media Independent
Interface) and 7-wire serial interfaces. It also provides describes operation and the
programming model.
Chapter 20, “Watchdog Timer
operation in low power mode.
Chapter 21, “Programmable Interrupt Timer Modules
functionality of the four PIT timers, including operation in low power mode.
Chapter 22, “DMA Timers
of the four DMA timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit
timers provide input capture and reference compare capabilities with optional signaling of
events using interrupts or triggers. This chapter also provides programming examples.
Chapter 23, “Queued Serial Peripheral Interface (QSPI)
overview and a description of operation, including details of the QSPI’s internal storage
organization. The chapter concludes with the programming model and a timing diagram.
Chapter 24, “UART
receiver/transmitters (UARTs) implemented on the MCF5271 and includes programming
examples.
Chapter 25, “I2C
clock synchronization, and I
programming examples.
Chapter 26, “Message Digest Hardware Accelerator
of two of the world’s most popular cryptographic hash functions: SHA-1 and MD5.
Accelerators for either algorithm separately have been designed, however the MDHA
combines similar functions of the two algorithms into one small, optimized area of silicon
on the MCF5271 device.
Chapter 27, “Random Number Generator (RNG),”
Generator (RNG), including a programming model, functional description, and application
information.
Chapter 28, “Symmetric Key Hardware Accelerator (SKHA),”
hardware coprocessor designed to implement two widely used symmetric key block cipher
algorithms, AES and DES.
Chapter 29, “IEEE 1149.1 Test Access Port
operation of the MCF5271 Joint Test Action Group (JTAG) implementation. It describes
those items required by the IEEE 1149.1 standard and provides additional information
specific to the MCF5271. For internal details and sample applications, see the IEEE 1149.1
document.
Interface,” describes the MCF5271 I
Modules,” describes the use of the universal asynchronous
MCF5271 Reference Manual, Rev. 2
(DTIM0–DTIM3),” describes the configuration and operation
2
C programming model registers. It also provides extensive
Module,” describes Watchdog timer functionality, including
(FEC),” provides a feature-set overview, a functional
(JTAG),” describes configuration and
describes the 32-bit Random Number
(MDHA),” describes implementation
(PIT0–PIT3),” describes the
2
C module, including I
Module,” provides a feature-set
describes the cryptographic
2
C protocol,
Organization
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