MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 541

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

29.1.3 Modes of Operation
The JTAG_EN pin can select between the following modes of operation:
29.2 External Signal Description
The JTAG module has five input and one output external signals, as described in
29.2.1 JTAG Enable (JTAG_EN)
The JTAG_EN pin selects between the Debug module and JTAG. If JTAG_EN is low, the Debug
module is selected; if it is high, the JTAG is selected.
selected depending upon JTAG_EN logic state.
When one module is selected, the inputs into the other module are disabled or forced to a known
logic level as shown in
Freescale Semiconductor
• JTAG mode
• BDM - background debug mode (For more information, refer to
TRST/DSCLK
TMS/BKPT
TDO/DSO
JTAG_EN
TDI/DSI
“Background Debug Mode
Name
TCLK
Module selected
Pin Function
Direction
Output
Input
Input
Input
Input
Input
Table
JTAG Test data output / BDM Development serial output
JTAG Test reset input / BDM Development serial clock
JTAG Test data input / BDM Development serial input
29-3, in order to disable the corresponding module.
Table 29-2. Pin Function Selected
Table 29-1. Signal Properties
JTAG Test mode select / BDM Breakpoint
MCF5271 Reference Manual, Rev. 2
(BDM)).”
JTAG_EN = 0
DSCLK
BKPT
JTAG/BDM selector input
BDM
DSO
DSI
—
JTAG Test clock input
Function
JTAG_EN = 1
Table 29-2
TCLK
TRST
JTAG
TMS
TDO
TDI
summarizes the pin function
Section 30.5,
Reset State
Pin Name
DSCLK
Hi-Z / 0
TCLK
BKPT
DSO
DSI
—
—
—
—
—
—
External Signal Description
Table
Pull up
Active
Active
Active
Active
29-1.
—
—
29-3