MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 211

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11.4.1 Overview
The SACU supports the traditional model of two privilege levels: supervisor and user. Typically,
memory references with the supervisor attribute have total accessibility to all the resources in the
system, while user mode references cannot access system control and configuration registers. In
many systems, the operating system executes in supervisor mode, while application software
executes in user mode.
The SACU further partitions the access control functions into two parts: one control register
defines the privilege level associated with each bus master, and another set of control registers
define the access levels associated with the peripheral modules and the memory space.
The SACU’s programming model is physically implemented as part of the System Control
Module (SCM) with the actual access control logic included as part of the arbitration controller.
Each bus transaction targeted for the IPS space is first checked to see if its privilege rights allow
access to the given memory space. If the privilege rights are correct, the access proceeds on the
bus. If the privilege rights are insufficient for the targeted memory space, the transfer is
immediately aborted and terminated with an exception, and the targeted module not accessed.
11.4.2 Features
Each bus transfer can be classified by its privilege level and the reference type. The complete set
of access types includes:
Instruction fetch accesses are associated with the execute attribute.
It should be noted that while the bus does not implement the concept of reference type (code versus
data) and only supports the user/supervisor privilege level, the reference type attribute is supported
by the system bus. Accordingly, the access checking associated with both privilege level and
reference type is performed in the IPS controller using the attributes associated with the reference
from the system bus.
The SACU partitions the access control mechanisms into three distinct functions:
Freescale Semiconductor
• Supervisor instruction fetch
• Supervisor operand read
• Supervisor operand write
• User instruction fetch
• User operand read
• User operand write
• Master privilege register (MPR)
— Allows each bus master to be assigned a privilege level:
– Disable the master’s user/supervisor attribute and force to user mode access
MCF5271 Reference Manual, Rev. 2
System Access Control Unit (SACU)
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