MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 510

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Message Digest Hardware Accelerator (MDHA)
followed in
of Key with OPAD.”
26.4.4
The HMAC/EHMAC is done in one step with the MACFULL bit.
26-18
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts.
3. MDMR register write. Select algorithm, data padding, and EHMAC.
4. Direct context load of (OPAD XOR key) into MDx1 registers from OPAD step.
5. MDMDS register write. Load this register with the length of the message from the OPAD
6. Direct context load of (IPAD XOR key) into MDx0 registers from IPAD step.
7. Direct context load of MDMDS register from the IPAD step (this should be 64 bytes).
8. Fill data FIFO with message to be hashed.
9. MDDSR register write. Load this register with the length of the message data (without
10. MDHA does the required algorithm’s auto padding of the message.
11. Set the MDCMR[GO] bit.
12. Wait for MDSR[DONE] to be set or done interrupt to be triggered to indicate successful
13. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, data padding, HMAC or EHMAC, and
4. Direct context load of key into MDx1 registers.
5. MDMDS register write. Load this register with the length of the key.
6. Fill data FIFO with message to be hashed.
step.
padding) in bits.
completion (or failure).
the message digest registers.
MACFULL bits.
Section 26.4.2.1, “Generation of Key with IPAD”
Performing a MAC Operation With the MACFULL Bit
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message
data. This will most likely occur if the MDDSR write is not received
or auto-padding is disabled and a partial message block is provided.
MCF5271 Reference Manual, Rev. 2
NOTE
and
Section 26.4.2.2, “Generation
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