MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 157

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7.4.6.2
In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode the current magnitude of
the charge pump varies with the MFD as shown in
The UP and DOWN signals from the PFD control whether the charge pump applies or removes
charge, respectively, from the loop filter. The filter is integrated on the chip.
7.4.6.3
The current into the ICO controls the frequency of the ICO output. The frequency-to-current
relationship (ICO gain) is positive.
7.4.6.4
When the PLL is not in 1:1 PLL mode, the MFD divides the output of the ICO and feeds it back
to the PFD. The PFD controls the ICO frequency via the charge pump and loop filter such that the
reference and feedback clocks have the same frequency and phase. Thus, the frequency of the
input to the MFD, which is also the output of the ICO, is the reference frequency multiplied by the
same amount that the MFD divides by. For example, if the MFD divides the ICO frequency by six,
the PLL is frequency locked when the ICO frequency is six times the reference frequency. The
presence of the MFD in the loop allows the PLL to perform frequency multiplication, or synthesis.
In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication factor is two.
7.4.6.5
The lock detect logic monitors the reference frequency and the PLL feedback frequency to
determine when frequency lock is achieved. Phase lock is inferred by the frequency relationship,
but is not guaranteed. The LOCK flag in the SYNSR reflects the PLL lock status. A sticky lock
flag, LOCKS, is also provided.
The lock detect function uses two counters. One is clocked by the reference and the other is
clocked by the PLL feedback. When the reference counter has counted N cycles, its count is
compared to that of the feedback counter. If the feedback counter has also counted N cycles, the
process is repeated for N + K counts. Then, if the two counters still match, the lock criteria is
relaxed by one count and the system is notified that the PLL has achieved frequency lock.
Freescale Semiconductor
Table 7-9. Charge Pump Current and MFD in Normal Mode Operation
Charge Pump/Loop Filter
Current Controlled Oscillator (ICO)
Multiplication Factor Divider (MFD)
PLL Lock Detection
Charge Pump Current
1X
2X
4X
MCF5271 Reference Manual, Rev. 2
Table
7-9.
0 ≤ MFD < 2
2 ≤ MFD < 6
6 ≤ MFD
MFD
Functional Description
7-23