MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 203

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

The physical base address programmed in both copies of the RAMBAR is typically the same
value; however, they can be programmed to different values. By definition, the base address must
be a 0-modulo-size value.
The SRAM module is configured through the RAMBAR shown in
Freescale Semiconductor
• RAMBAR specifies the base address of the SRAM.
• All undefined bits are reserved. These bits are ignored during writes to the RAMBAR and
• The back door enable bit, RAMBAR[BDE], is cleared at reset, disabling the DMA module
Address
Reset
Reset
31–16
15–10
return zeros when read.
access to the SRAM.
Bits
8–0
9
W
W
R
R
31
15
0
0
0
Name
BDE
30
14
0
0
0
BA
Figure 11-2. Memory Base Address Register (RAMBAR)
—
—
29
13
0
0
0
Base address. Defines the memory module's base address on a 64-Kbyte boundary
corresponding to the physical array location within the 4 Gbyte address space supported
by ColdFire.
Reserved, should be cleared.
Back door enable. Qualifies the DMA module accesses to the SRAM memory.
0 Disables DMA module accesses to the SRAM module.
1 Enables DMA module accesses to the SRAM module.
NOTE: The SPV bit in the CPU’s RAMBAR must also be set to allow dual port access to
the SRAM. For more information, see
(RAMBAR).”
Reserved, should be cleared.
Table 11-3. RAMBAR Field Description
28
12
0
0
0
27
11
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
0
0
0
BDE
25
0
0
9
IPSBAR + 0x008
24
0
0
0
8
BA
23
Section 6.2.1, “SRAM Base Address Register
Description
0
0
0
7
22
0
6
0
0
21
0
0
0
5
Figure
20
0
0
0
4
Memory Map/Register Definition
11-2.
19
0
0
0
3
18
0
0
0
2
17
0
0
0
1
16
0
0
0
0
11-5