MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 140

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Clock Module
output. Consequently, frequency modulation is not available. To enter external clock mode, the
PLL must be set by following the procedure outlined in
7.1.3.5
This subsection describes the operation of the clock module in low-power and halted modes of
operation. Low-power modes are described in
the clock module operation in low-power modes.
In wait and doze modes, the system clocks to the peripherals are enabled, and the clocks to the
CPU, and SRAM are stopped. Each module can disable its clock locally at the module level.
During stop mode, the PLL continues to run. The external CLKOUT signal may be enabled or
disabled when the device enters stop mode, depending on the LPCR[STPMD] bit settings.
The external CLKOUT output pin may be disabled to lower power consumption via the
SYNCR[DISCLK] bit. The external CLKOUT pin function is enabled by default at reset.
7.2
The clock module signals are summarized in
detailed information, refer to
7-6
Low-power Mode
External Signal Descriptions
Doze
Wait
Stop
Low-power Mode Operation
XTAL must be tied low in external clock mode when reset is asserted.
If it is not, clocks could be suspended indefinitely.
Table 7-1. Clock Module Operation in Low-power Modes
EXTAL
XTAL
CLKOUT
All system clocks disabled, but clock module
Clocks sent to peripheral modules only
Clocks sent to peripheral modules only
Name
Chapter 14, “Signal
Clock Operation
continues to run
Table 7-2. Signal Properties
MCF5271 Reference Manual, Rev. 2
Oscillator or clock input
Oscillator output
Internal bus clock output
NOTE
Table 7-2
Chapter 8, “Power
Descriptions.”
Function
Section 7.4.3, “System Clock Generation.”
and a brief description follows. For more
Exit not caused by clock module, but normal
Exit not caused by clock module, but normal
sources are re-enabled and normal clocking
Exit not caused by clock module, but clock
clocking resumes upon mode exit
clocking resumes upon mode exit
Management.”
resumes upon mode exit
Mode Exit
Freescale Semiconductor
Table 7-1
shows

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