MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 326

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Synchronous DRAM Controller Module
18-8
10–8
Bits
5–4
2–0
7
6
3
Name
IMRS
CBM
PS
—
IP
—
Table 18-5. DACRn Field Descriptions (Continued)
Command and bank MUX [2:0]. Because different SDRAM configurations cause the
command and bank select lines to correspond to different addresses, these resources are
programmable. CBM determines the addresses onto which these functions are multiplexed.
This encoding and the address multiplexing scheme handle common SDRAM organizations.
Bank select bits include a base bit and all address bits above for SDRAMs with multiple bank
select bits.
Reserved, should be cleared.
Initiate mode register set (
associated SDRAMs. In initialization, IMRS should be set only after all DRAM controller
registers are initialized and
the next access to an SDRAM block programs the SDRAM’s mode register. Thus, the address
of the access should be programmed to place the correct mode information on the SDRAM
address pins. Because the SDRAM does not register this information, it doesn’t matter if the
IMRS access is a read or a write or what, if any, data is put onto the data bus. The DRAM
controller clears IMRS after the
0 Take no action
1 Initiate
Port size. Indicates the port size of the associated block of SDRAM, which allows for dynamic
sizing of associated SDRAM accesses. PS functions the same in asynchronous operation.
00 32-bit port
01 8-bit port
1x 16-bit port
Initiate precharge all (
is finished. Accesses via IP should be no wider than the port size programmed in PS.
0 Take no action.
1 A
Reserved, should be cleared.
command is executed after all DRAM controller registers are programmed. After IP is set,
the next write to an appropriate SDRAM address generates the
SDRAM block.
PALL
command is sent to the associated SDRAM block. During initialization, this
MRS
MCF5271 Reference Manual, Rev. 2
command
PALL
CBM
000
001
010
100
101
011
110
111
) command. The DRAM controller clears IP after the
MRS
PALL
) command. Setting IMRS generates a
and
MRS
REFRESH
command finishes.
Command Bit
Description
17
18
19
20
21
22
23
24
commands have been issued. After IMRS is set,
Bank Select Bits
18 and up
19 and up
20 and up
21 and up
22 and up
23 and up
24 and up
25 and up
PALL
MRS
Freescale Semiconductor
command to the
command to the
PALL
command