MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 318

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

External Interface Module (EIM)
17.7 Misaligned Operands
Because operands can reside at any byte boundary, unlike opcodes, they are allowed to be
misaligned. A byte operand is properly aligned at any address, a word operand is misaligned at an
odd address, and a longword is misaligned at an address not a multiple of four. Although the
MCF5271 enforces no alignment restrictions for data operands (including program counter (PC)
relative data addressing), additional bus cycles are required for misaligned operands.
Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to
prefetch a misaligned instruction word causes an address error exception.
The MCF5271 converts misaligned, cache-inhibited operand accesses to multiple aligned
accesses.
port. In this example, TSIZ[1:0] specify a byte transfer and a byte offset of 0x1. The slave device
supplies the byte and acknowledges the data transfer. When the MCF5271 starts the second cycle,
TSIZ[1:0] specify a word transfer with a byte offset of 0x2. The next two bytes are transferred in
this cycle. In the third cycle, byte 3 is transferred. The byte offset is now 0x0, the port supplies the
final byte, and the operation is complete.
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded
into the cache. The example in
is word-sized and the transfer takes only two bus cycles.
17-16
Transfer 1
Transfer 2
Transfer 1
Transfer 2
Transfer 3
Figure 17-19
Figure 17-19. Example of a Misaligned Longword Transfer (32-Bit Port)
Figure 17-20. Example of a Misaligned Word Transfer (32-Bit Port)
31
31
shows the transfer of a longword operand from a byte address to a 32-bit
Byte 1
Byte 3
—
—
—
Figure 17-20
24 23
24 23
MCF5271 Reference Manual, Rev. 2
Byte 0
—
—
—
—
differs from that in
16 15
16 15
Byte 1
—
—
—
—
8 7
8 7
Figure 17-19
Byte 0
Byte 2
—
—
—
0
0
Freescale Semiconductor
in that the operand
A[2:0]
A[2:0]
001
100
001
010
100