MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 290

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Edge Port Module (EPORT)
15.4.1.5 Edge Port Pin Data Register (EPPDR)
15.4.1.6 Edge Port Flag Register (EPFR)
15-6
Bits
Bits
7–1
7–1
0
0
EPPDn
Name
Name
EPFn
Address
Address
—
—
Reset
Reset
Figure 15-6. EPORT Port Pin Data Register (EPPDR)
W
W
R EPPD7 EPPD6 EPPD5 EPPD4 EPPD3 EPPD2 EPPD1
R EPF7
Figure 15-7. EPORT Port Flag Register (EPFR)
Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins
IRQ7–IRQ1. Writing to EPPDR has no effect, and the write cycle terminates normally.
Reset does not affect EPPDR.
Reserved, should be cleared.
Edge port flag bits. When an EPORT pin is configured for edge triggering, its
corresponding read/write bit in EPFR indicates that the selected edge has been detected.
Reset clears EPF7–EPF1.
Bits in this register are set when the selected edge is detected on the corresponding pin.
A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect. If a pin is
configured as level-sensitive (EPPARn = 00), pin transitions do not affect this register.
0 Selected edge for IRQn pin has not been detected.
1 Selected edge for IRQn pin has been detected.
Reserved, should be cleared.
0
7
7
Table 15-7. EPPDR Field Descriptions
Table 15-8. EPFR Field Descriptions
EPF6
MCF5271 Reference Manual, Rev. 2
0
6
6
EPF5
0
5
5
Current pin state
IPSBAR + 0x13_0005
IPSBAR + 0x13_0006
EPF4
0
4
4
EPF3
Description
Description
0
3
3
EPF2
2
2
0
EPF1
0
1
1
0
0
0
0
0
0
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