MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 587

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Table 30-4
Command Sequence:
Operand Data:
Result Data:
30.6
The ColdFire Family provides support debugging real-time applications. For these types of
embedded systems, the processor must continue to operate during debug. The foundation of this
area of debug support is that while the processor cannot be halted to allow debugging, the system
can generally tolerate small intrusions into the real-time operation.
The debug module provides three types of breakpoints—PC with mask, operand address range,
and data with mask. These breakpoints can be configured into one- or two-level triggers with the
exact trigger response also programmable. The debug module programming model can be written
from either the external development system using the debug serial interface or from the
processor’s supervisor programming model using the WDEBUG instruction. Only CSR is
readable using the external development system.
30.6.1 Theory of Operation
Breakpoint hardware can be configured to respond to triggers in several ways. The response
desired is programmed into TDR. As shown in
indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying
captured processor status, operands, or branch addresses.
Freescale Semiconductor
Real-Time Debug Support
shows the definition of the DRc write encoding.
WDMREG
???
Longword data is written into the specified debug register. The data is
supplied most-significant word first.
Command complete status (0xFFFF) is returned when register write is
complete.
Figure 30-40.
’NOT READY’
MCF5271 Reference Manual, Rev. 2
’ILLEGAL’
MS DATA
XXX
WDMREG
Table
Command Sequence
’NOT READY’
’NOT READY’
NEXT CMD
LS DATA
30-22, when a breakpoint is triggered, an
’CMD COMPLETE’
NEXT CMD
Real-Time Debug Support
30-37