MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 232

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

General Purpose I/O Module
12.3.1.4 Port Clear Output Data Registers (PCLRR_x)
Clearing a PCLRR_x register clears the corresponding bits in the PODR_x register. Setting it has
no effect. Reading the PCLRR_x register returns 0s. Most PODR_x registers have a full 8-bit
implementation, as shown in
bits. Their bit definitions are shown in
The PCLRR_x registers are read/write accessible.
12-16
Figure 12-21. Port UARTH Pin Data/Set Data Register (PPDSDR_UARTH)
Figure 12-22. Port QSPI Pin Data/Set Data Register (PPDSDR_QSPI)
Address
Reset
Note: See above figures for bit field positions.
W
R
Figure 12-23. Port Clear Output Data Registers (PCLRR_x)
Address
Address
PPDSDR_x
Reset
Reset
Name
IPSBAR + 0x10_0033 (PCLRR_BUSCTL); IPSBAR + 0x10_0039 (PCLRR_UARTL);
IPSBAR + 0x10_0031 (PCLRR_DATAH); IPSBAR + 0x10_0032 (PCLRR_DATAL);
—
W
0
0
R
7
W
R
Table 12-6. PPDSDR_x Field Descriptions
0
0
7
0
0
7
Figure
Reserved, should be cleared.
Port x Pin Data/Set Data Bits.
0 Port x pin state is 0 (read)
1 Port x pin state is 1 (read); set corresponding PODR_x bit (write)
0
0
6
0
0
6
MCF5271 Reference Manual, Rev. 2
0
0
6
IPSBAR + 0x10_0028 (PPDSDR_UARTH)
12-23. The remaining PODR_x registers use fewer than eight
IPSBAR + 0x10_002A (PPDSDR_QSPI)
IPSBAR + 0x10_003B (PCLRR_TIMER)
Figure 12-24
0
0
5
0
0
5
0
0
5
0
0
4
0
0
4
4
PCLRR_x
Description
through
0
0
3
3
0
0
Current Pin State
3
PPDSDR_QSPI
Figure
0
0
2
2
0
0
2
PPDSDR_UARTH
Current pin state
12-29.
1
1
0
0
1
0
0
Freescale Semiconductor
0
0
0