MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 289

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

15.4.1.3 Edge Port Interrupt Enable Register (EPIER)
15.4.1.4 Edge Port Data Register (EPDR)
Freescale Semiconductor
Bits
Bits
7–1
7–1
0
0
Figure 15-4. EPORT Port Interrupt Enable Register (EPIER)
EPIEn
Name
Name
EPDn
Address
Address
—
—
Reset
Reset
W
W
R EPIE7
R EPD7
Figure 15-5. EPORT Port Data Register (EPDR)
Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set,
EPORT generates an interrupt request when:
Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin.
Reset clears EPIE7–EPIE1.
0 Interrupt requests from corresponding EPORT pin disabled
1 Interrupt requests from corresponding EPORT pin enabled
Reserved, should be cleared.
Edge port data bits. Data written to EPDR is stored in an internal register; if any pin of the
port is configured as an output, the bit stored for that pin is driven onto the pin. Reading
EDPR returns the data stored in the register. Reset sets EPD7–EPD1.
Reserved, should be cleared.
• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set.
• The corresponding pin level is low and the pin is configured for level-sensitive operation.
0
1
7
7
Table 15-5. EPIER Field Descriptions
Table 15-6. EPDR Field Descriptions
EPIE6
EPD6
MCF5271 Reference Manual, Rev. 2
0
1
6
6
EPIE5
EPD5
0
1
5
5
IPSBAR + 0x13_0003
IPSBAR + 0x13_0004
EPIE4
EPD4
0
1
4
4
EPIE3
EPD3
Description
Description
0
1
3
3
EPIE2
EPD2
2
0
2
1
EPIE1
EPD1
0
1
1
1
Memory Map/Register Definition
0
0
0
1
0
0
15-5