MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 159

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MFD. If the PLL is intentionally disabled during stop mode, then after exit from stop mode, the
LOCKS flag reflects the value prior to entering stop mode once lock is regained.
7.4.6.7
If the LOLRE bit in the SYNCR is set, a loss-of-lock condition asserts reset. Reset reinitializes the
LOCK and LOCKS flags. Therefore, software must read the LOL bit in the reset status register
(RSR) to determine if a loss-of-lock caused the reset. See
(RSR).”
To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock.
In external clock mode, the PLL cannot lock. Therefore, a loss-of-lock condition cannot occur, and
the LOLRE bit has no effect.
7.4.6.8
The PLL provides the ability to request an interrupt when a loss-of-lock condition occurs by
programming the LOLIRQ bit in the SYNCR. An interrupt is requested by the PLL if LOLIRQ is
set.
In external clock mode, the PLL cannot lock. Therefore, a loss-of-lock condition cannot occur, and
the LOLIRQ bit has no effect.
7.4.6.9
The LOCEN bit in the SYNCR enables the loss-of-clock detection circuit to monitor the input
clocks to the phase and frequency detector (PFD). When either the reference or feedback clock
frequency falls below the minimum frequency (see electrical specification for this value), the
loss-of-clock circuit sets the sticky LOCF bit, and non-sticky LOC bit, in the SYNSR.
In external clock mode, the loss-of-clock circuit is disabled.
7.4.6.10 Loss-of-Clock Reset
The clock module can assert a reset when a loss-of-clock or loss-of-lock occurs. When a
loss-of-clock condition is recognized, reset is asserted if the LOCRE bit in SYNCR is set. The
LOCS bit in SYNSR is cleared after reset. Therefore, the LOC bit must be read in the RSR to
determine that a loss-of-clock condition occurred. LOCRE has no effect in external clock mode.
To exit reset in PLL mode, the reference must be present, and the PLL must acquire lock.
Reset initializes the clock module registers to a known startup state as described in
“Memory Map/Register
Freescale Semiconductor
PLL Loss-of-Lock Reset
PLL Loss-of-Lock Interrupt Request
Loss-of-Clock Detection
Definition.”
MCF5271 Reference Manual, Rev. 2
Section 10.3.2, “Reset Status Register
Functional Description
Section 7.3,
7-25