MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 128

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Cache
5-12
Bits
4–3
1–0
5
2
Name
BWE
WP
—
—
Table 5-7. ACR Field Descriptions (Continued)
Buffered write enable. This bit defines the value for enabling buffered writes. If BWE = 0,
the termination of an operand write cycle on the processor's local bus is delayed until the
external bus cycle is completed. If BWE = 1, the write cycle on the local bus is terminated
immediately and the operation is then buffered in the bus controller. In this mode, operand
write cycles are effectively decoupled between the processor's local bus and the external
bus.
Generally, the enabling of buffered writes provides higher system performance but
recovery from access errors may be more difficult. For the V2 ColdFire core, the reporting
of access errors on operand writes is always imprecise, and enabling buffered writes
simply decouples the write instruction from the signaling of the fault even more.
0 Writes are not buffered.
1 Writes are buffered.
Reserved, should be cleared.
Write protect. The WP bit defines the write-protection attribute. If the effective memory
attributes for a given access select the WP bit, an access error terminates any attempted
write with this bit set.
0 Read and write accesses permitted
1 Only read accesses permitted
Reserved, should be cleared.
MCF5271 Reference Manual, Rev. 2
Description
Freescale Semiconductor