MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 62

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Signal Descriptions
2.3.10 UART Module Signals
The UART modules use the signals in this section for data. The baud rate clock inputs are not
supported.
2.3.11 DMA Timer Signals
Table 2-12
2-12
QSPI Syncrhonous
Serial Output
QSPI Synchronous
Serial Data Input
QSPI Serial Clock
Synchronous
Peripheral Chip Selects
Transmit Serial Data
Output
Receive Serial Data
Input
Clear-to-Send
Request-to-Send
Signal Name
Signal Name
describes the signals of the four DMA timer modules.
Table 2-10. Queued Serial Peripheral Interface (QSPI) Signals
QSPI_DOUT
QSPI_DIN
QSPI_CLK
QSPI_CS[1:0] Provide QSPI peripheral chip selects that can be programmed to be
U2TXD/U1TXD
/U0TXD
U2RXD/U1RX
D/U0RXD
U1CTS/U0CTS Indicate to the UART modules that they can begin data transmission.
U1RTS/U0RTS Automatic request-to-send outputs from the UART modules.
Abbreviation
Abbreviation
Table 2-11. UART Module Signals
MCF5271 Reference Manual, Rev. 2
Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK. Each byte is sent
msb first.
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK. Each byte is
written to RAM lsb first.
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable. The output frequency is programmed
according to the following formula, in which n can be any value
between 1 and 255:
active high or low. QSPI_CS1 can also be configured as SDRAM
clock enable signal SD_CKE.
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, lsb first, on this pin at the
falling edge of the serial clock source.
Receiver serial data inputs for the UART modules. Data received on
this pin is sampled on the rising edge of the serial clock source lsb
first. When the UART clock is stopped for power-down mode, any
transition on this pin restarts it.
U1RTS/U0RTS can also be configured to be asserted and negated as
a function of the RxFIFO level.
SPI_CLK = f
Function
Function
sys/2
÷ (2 × n)
Freescale Semiconductor
I/O
I/O
O
O
O
O
O
I
I
I