MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 589

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

When debug interrupt operations complete, the RTE instruction executes and the processor exits
emulator mode. After the debug interrupt handler completes execution, the external development
system can use BDM commands to read the reserved memory locations.
If a hardware breakpoint such as a PC trigger is left unmodified by the debug interrupt service
routine, another debug interrupt is generated after the completion of the RTE instruction.
30.6.1.1 Emulator Mode
Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be entered
in three different ways:
While operating in emulation mode, the processor exhibits the following properties:
The RTE instruction exits emulation mode. The processor status output port provides a unique
encoding for emulator mode entry (0xD) and exit (0x7).
30.6.2 Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM commands.
BDM commands may be executed while the processor is running, except those following
operations that access processor/memory registers:
For BDM commands that access memory, the debug module requests the processor’s local bus.
The processor responds by stalling the instruction fetch pipeline and waiting for current bus
activity to complete before freeing the local bus for the debug module to perform its access. After
the debug module bus cycle, the processor reclaims the bus.
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• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if
• A debug interrupt always puts the processor in emulation mode when debug interrupt
• Setting CSR[TRC] forces the processor into emulation mode when trace exception
• All interrupts are ignored, including level-7 interrupts.
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory
• Read/write address and data registers
• Read/write control registers
RESET is negated and the processor begins reset exception processing. It can be set while
the processor is halted before reset exception processing begins. See
Halt.”
exception processing begins.
processing begins.
accesses are forced into a specially mapped address space signaled by TT = 0x2, TM = 0x5
or 0x6. This includes stack frame writes and the vector fetch for the exception that forced
entry into this mode.
MCF5271 Reference Manual, Rev. 2
Section 30.5.1, “CPU
Real-Time Debug Support
30-39