MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 368
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Fast Ethernet Controller (FEC)
19.2.4.17 Descriptor Group Lower Address Register (GALR)
The GALR register is written by the user. This register contains the lower 32 bits of the 64-bit hash
table used in the address recognition process for receive frames with a multicast address. This
register must be initialized by the user.
19.2.4.18 FIFO Transmit FIFO Watermark Register (TFWR)
The TFWR is a 2-bit read/write register programmed by the user to control the amount of data
required in the transmit FIFO before transmission of a frame can begin. This allows the user to
minimize transmit latency (TFWR = 0x) or allow for larger bus access latency (TFWR = 11) due
to contention for the system bus. Setting the watermark to a high value will minimize the risk of
transmit FIFO underrun due to contention for the system bus. The byte counts associated with the
TFWR field may need to be modified to match a given system requirement (worst case bus access
latency by the transmit data DMA channel).
19-24
Address
Reset
Reset
31–0
31–0
Bits
Bits
W
W
R
R
—
—
31
15
Figure 19-18. Descriptor Group Lower Address Register (GALR)
GADDR1
GADDR2
Name
Name
—
—
30
14
—
—
29
13
The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the
address recognition process for receive frames with a multicast address. Bit 31 of
GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the
address recognition process for receive frames with a multicast address. Bit 31 of
GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
—
—
Table 19-20. GAUR Field Descriptions
28
12
Table 19-21. GALR Field Descriptions
—
—
27
11
MCF5271 Reference Manual, Rev. 2
—
—
26
10
25
—
—
9
IPSBAR + 0x1124
GADDR2
GADDR2
—
—
24
8
23
—
—
Description
Description
7
—
—
22
6
—
—
21
5
—
—
20
4
—
—
19
3
Freescale Semiconductor
—
—
18
2
—
—
17
1
16
—
—
0
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