MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 322

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Synchronous DRAM Controller Module
SDRAMs operate differently than asynchronous DRAMs, particularly in the use of data pipelines
and commands to initiate special actions. Commands are issued to memory using specific
encodings on address and control pins. Soon after system reset, a command must be sent to the
SDRAM mode register to configure SDRAM operating parameters.
18.2
Table 18-2
18-4
SD_SRAS
SD_SCAS
SD_WE
SD_CS[1:0]
SD_CKE
BS[3:0]
OE
Command
WRITE
SELFX
READ
PALL
SELF
REF
Signal
External Signal Description
describes the behavior of DRAM signals in synchronous mode.
Precharge all. Precharges all internal banks of an SDRAM component; executed before new page is
opened.
Read access. SDRAM registers column address and decodes that a read access is occurring.
Refresh. Refreshes internal bank rows of an SDRAM component.
Self refresh. Refreshes internal bank rows of an SDRAM component when it is in low-power mode.
Exit self refresh. This command is sent to the DRAM controller when DCR[IS] is cleared.
Write access. SDRAM registers column address and decodes that a write access is occurring.
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS.
Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding SDRAM SD_SCAS.
SDRAM read/write. Asserted for write operations and negated for read operations.
Select each memory block of SDRAMs connected to the MCF5271. One SD_CS signal selects
one SDRAM block and connects to the corresponding CS signals.
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is deasserted, memory
can enter a power-down mode in which operations are suspended or capable of entering
self-refresh mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external
multiplexing, setting COC allows SD_CKE to provide command-bit functionality.
BS[3:0] function as byte enables to the SDRAMs. They connect to the BS signals (or mask
qualifiers) of the SDRAMs.
Output Enable for SDRAM write data. During a write to the SDRAM, OE will be asserted during
the time that data is valid. This signal could be used to control the three-stating and activation of
the on-chip I/O buffers that are connected to the SDRAM data (Q) lines. This signal is low during
SDRAM reads. Do not confuse this signal with BS.
Table 18-2. Synchronous DRAM Signal Connections
Table 18-1. SDRAM Commands (Continued)
MCF5271 Reference Manual, Rev. 2
Definition
Description
Freescale Semiconductor