MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 384
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Fast Ethernet Controller (FEC)
If the DA is a group (multicast) address and flow control is disabled, then the microcontroller will
perform a group hash table lookup using the 64-entry hash table programmed in GAUR and
GALR. If a hash match occurs, the receiver accepts the frame.
If flow control is enabled, the microcontroller will do an exact address match check between the
DA and the designated PAUSE DA (01:80:C2:00:00:01). If the receive block determines that the
received frame is a valid PAUSE frame, then the frame will be rejected. Note the receiver will
detect a PAUSE frame with the DA field set to either the designated PAUSE DA or the unicast
physical address.
If the DA is the individual (unicast) address, the microcontroller performs an individual exact
match comparison between the DA and 48-bit physical address that the user programs in the PALR
and PAUR registers. If an exact match occurs, the frame is accepted; otherwise, the
microcontroller does an individual hash table lookup using the 64-entry hash table programmed in
registers, IAUR and IALR. In the case of an individual hash match, the frame is accepted. Again,
the receiver will accept or reject the frame based on PAUSE frame detection, shown in
Figure
19-27.
If neither a hash match (group or individual), nor an exact match (group or individual) occur, then
if promiscuous mode is enabled (RCR[PROM] = 1), then the frame will be accepted and the MISS
bit in the receive buffer descriptor is set; otherwise, the frame will be rejected.
Similarly, if the DA is a broadcast address, broadcast reject (RCR[BC_REJ]) is asserted, and
promiscuous mode is enabled, then the frame will be accepted and the MISS bit in the receive
buffer descriptor is set; otherwise, the frame will be rejected.
In general, when a frame is rejected, it is flushed from the FIFO.
MCF5271 Reference Manual, Rev. 2
19-40
Freescale Semiconductor
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