MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 230

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

General Purpose I/O Module
12.3.1.3 Port Pin Data/Set Data Registers (PPDSDR_x)
The PPDSDR_x registers reflect the current pin states and control the setting of output pins when
the pin is configured for general purpose I/O. The PPDSDR_x registers are each eight bits wide,
but not all ports use all eight bits. The register definitions for all ports are shown in
through
The PPDSDR_x registers are read/write. At reset, the bits in the PPDSDR_x registers are set to the
current pin states. Reading a PPDSDR_x register returns the current state of the port x pins. Setting
a PPDSDR_x register sets the corresponding bits in the PODR_x register. Writing 0s has no effect.
12-14
Figure
Figure 12-14. Port UARTH Data Direction Register (PDDR_UARTH)
Figure 12-15. Port QSPI Data Direction Register (PDDR_QSPI)
12-22.
Address
Address
Reset
Reset
Note: See above figures for bit field positions.
W
W
R
R
PDDR_x
Name
—
0
0
0
0
7
7
Table 12-5. PDDR_x Field Descriptions
MCF5271 Reference Manual, Rev. 2
0
0
0
0
6
6
Reserved, should be cleared.
Port x output data direction bits.
1 Port x pin configured as output
0 Port x pin configured as input
IPSBAR + 0x10_0018 (PDDR_UARTH)
IPSBAR + 0x10_001A (PDDR_QSPI)
0
0
0
0
5
5
0
0
0
4
4
Description
0
0
0
3
3
PDDR_QSPI
2
0
0
2
0
PDDR_UARTH
0
0
1
1
0
0
0
0
Freescale Semiconductor
Figure 12-16