MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 129

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 6
Static RAM (SRAM)
6.1
This chapter is a description of the on-chip static RAM (SRAM) implementation that covers
general operations, configuration, and initialization. It also provides information and examples
showing how to minimize power consumption when using the SRAM.
6.1.1
6.1.2
The SRAM module provides a general-purpose memory block that the ColdFire processor can
access in a single cycle. The location of the memory block can be specified to any 0-modulo-64K
address within the 4-Gbyte address space. The memory is ideal for storing critical code or data
structures or for use as the system stack. Because the SRAM module is physically connected to
the processor's high-speed local bus, it can service processor-initiated access or
memory-referencing commands from the debug module.
Depending on configuration information, instruction fetches may be sent to both the cache and the
SRAM block simultaneously. If the reference is mapped into the region defined by the SRAM, the
SRAM provides the data back to the processor, and the cache data is discarded. Accesses from the
SRAM module are not cached.
The SRAM is dual-ported to provide DMA or FEC access. The SRAM is partitioned into two
physical memory arrays to allow simultaneous access to both arrays by the processor core and
another bus master. See
6.2
The SRAM programming model includes a description of the SRAM base address register
(RAMBAR), SRAM initialization, and power management.
Freescale Semiconductor
• One 64-Kbyte SRAM
• Single-cycle access
• Physically located on processor's high-speed local bus
• Memory location programmable on any 0-modulo-64 Kbyte address
• Byte, word, longword address capabilities
Introduction
Features
Operation
Register Description
Section 11.3, “Internal Bus Arbitration,”
MCF5271 Reference Manual, Rev. 2
for more information.
6-1