MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 341

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

18.4.4 DMR Initialization
Again, in this example only the second 512-Kbyte block of each 1-Mbyte space is accessed in each
bank. In addition, the SDRAM component is mapped only to readable and writable supervisor and
user data. The DMRs have the following configuration.
With this configuration, the DMR0 = 0x0074_0001, as described in
Freescale Semiconductor
31–18
17–16
Setting
Setting
15–9
Bits
7-1
8
0
(hex)
(hex)
Field
Field
Name
BAM
WP
Bits
—
31
15
5–4
2–0
—
—
—
0
0
V
3
—
30
14
0
0
0000_000
0000_000
Name
Setting
Table 18-28. DACR Initialization Values (Continued)
0
0
PS
IP
—
00
0
1
—
29
13
0
0
Table 18-29. DMR0 Initialization Values
—
28
12
0
0
Setting
With bits 17 and 16 as don’t cares, BAM = 0x0074, which leaves bank select bits
and upper 512K select bits unmasked. Note that bits 22 and 21 are set because they
are used as bank selects; bit 20 is set because it controls the 1-Mbyte boundary
address.
Reserved.
Reserved.
Allow reads and writes
Reserved.
Enable accesses.
000
00
0
Figure 18-14. DMR0 Register
—
27
11
0
0
MCF5271 Reference Manual, Rev. 2
32-bit port.
Indicates precharge has not been initiated.
Reserved.
—
26
10
0
0
0
0
25
—
0
0
9
BAM
WP
24
0
0
8
—
23
0
0
7
Description
Description
—
22
1
0
6
7
0
—
21
1
0
5
Table
—
20
1
0
4
—
19
18-29.
0
0
3
—
18
1
2
0
4
1
—
—
SDRAM Example
17
0
0
1
—
16
V
0
1
0
18-23