MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 586
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Debug Support
Table 30-21
Command Sequence:
Operand Data:
Result Data:
30.5.3.3.12Write Debug Module Register (
The operand (longword) data is written to the specified debug module register. All 32 bits of the
register are altered by the write. DSCLK must be inactive while the debug module register writes
from the CPU accesses are performed using the WDEBUG instruction.
Command Format:
30-36
Command
0x01–0x1F
15
DRc[4:0]
0x00
Result
14
shows the definition of DRc encoding.
0x2
15
13
14
Figure 30-37.
None
The contents of the selected debug register are returned as a longword value.
The data is returned most-significant word first.
Debug Register Definition
0x2
Table 30-21. Definition of DRc Encoding—Read
12
Figure 30-39.
Figure 30-38.
Configuration/Status
13
11
RDMREG
Reserved
12
???
10
MCF5271 Reference Manual, Rev. 2
11
0xC
RDMREG
WDMREG
9
RDMREG
10
0xD
MS RESULT
’ILLEGAL’
D[31:16]
8
9
D[15:0]
Command/Result Formats
XXX
XXX
BDM Command Format
Command Sequence
WDMREG
D[31:16]
8
D[15:0]
7
Mnemonic
7
100
CSR
6
—
)
100
’NOT READY’
6
LS RESULT
NEXT CMD
NEXT CMD
5
5
4
Initial State
4
0x0
—
3
3
DRc
Freescale Semiconductor
DR
2
2
c
1
1
p. 30-9
Page
—
0
0
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