MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 123

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.2.1
5.2.1.1
The CACR controls the operation of the cache. The CACR provides a set of default memory
access attributes used when a reference address does not map into the spaces defined by the ACRs.
The CACR is a 32-bit write-only supervisor control register. It is accessed in the CPU address
space via the MOVEC instruction with an Rc encoding of 0x002. The CACR can be read when in
background debug mode (BDM). At system reset, the entire register is cleared.
Freescale Semiconductor
Address
• Addresses not assigned to the registers and undefined register bits are reserved for future
• The reset value column indicates the register initial value at reset. Certain registers may be
• The access column indicates if the corresponding register allows both read/write
Reset
Reset
expansion. The user should write zeros to these reserved address spaces and read accesses
will return zeros.
uninitialized upon reset; that is, they may contain random values after reset.
functionality (R/W), read-only functionality (R), or write-only functionality (W). If a read
access to a write-only register is attempted, zeros will be returned. If a write access to a
read-only register is attempted, the access will be ignored and no write will occur.
W CENB
W
R
R
MOVEC with 0x002
MOVEC with 0x004
MOVEC with 0x005
1
Registers Description
Readable through debug
Cache Control Register (CACR)
31
15
0
0
Address
30
14
0
0
—
—
29
13
0
0
Table 5-3. Memory Map of Cache Registers
Figure 5-2. Cache Control Register (CACR)
CPD CFRZ
28
12
0
0
CACR
Name
ACR0
ACR1
27
11
0
0
MCF5271 Reference Manual, Rev. 2
Width
CEIB DCM DBWE
26
10
32
32
32
0
0
—
Cache Control Register
Access Control Register 0
Access Control Register 1
25
0
0
9
MOVEC with 0x002
CINV
24
0
0
8
Description
DISI DISD INVI INVD
23
0
0
7
—
22
0
0
6
DWP EUSP
21
0
0
5
0x0000_0000
0x0000_0000
0x0000_0000
Reset Value
20
0
4
0
Memory Map/Register Definition
19
0
0
3
—
18
0
0
2
Access
—
W
W
W
1
17
0
0
1
CLNF
16
0
0
0
5-7