MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 451
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24.3.8
The UIPCRs, shown in
24.3.9
The UACRs, shown in
Freescale Semiconductor
Bits
7–5
3–1
4
0
UART Input Port Change Registers (UIPCRn)
UART Auxiliary Control Register (UACRn)
Name
Figure 24-10. UART Input Port Change Register (UIPCRn)
COS
CTS
Address
Address IPSBAR + 0x0210 (UIPCR0); IPSBAR + 0x0250 (UIPCR1); IPSBAR +
—
—
Reset
Reset
W
W
R
R
Figure
Figure
Reserved, should be cleared.
Change of state (high-to-low or low-to-high transition).
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears
1 A change-of-state longer than 25–50 µs occurred on the UnCTS input. UACRn can be
Reserved, should be cleared.
Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the
state of UnCTS. If UnCTS is detected asserted at that time, COS is set, which initiates an
interrupt if UACRn[IEC] is enabled.
0 The current state of the UnCTS input is asserted.
1 The current state of the UnCTS input is deasserted.
Figure 24-9. UART Transmit Buffer (UTBn)
UISRn[COS].
programmed to generate an interrupt to the CPU when a change of state is detected.
0
0
0
7
7
Table 24-8. UIPCRn Field Descriptions
24-8, control the input enable.
24-10, hold the current state and the change-of-state for UnCTS.
IPSBAR + 0x020C(UTB0); IPSBAR + 0x024C(UTB1);
MCF5271 Reference Manual, Rev. 2
0
0
0
6
6
0
0
0
5
5
IPSBAR + 0x028C(UTB2)
0x0290 (UIPCR2)
COS
0
0
4
4
TB
Description
0
0
1
3
3
2
0
2
0
1
0
0
1
1
1
Memory Map/Register Definition
UnCTS
CTS
0
0
0
24-13
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