MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 171

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

When stop mode is exited clearing the DCR[IS] bit will cause the SDRAM to exit the self-refresh
mode and allow bus cycles to the SDRAM to resume.
8.3.2.5
In wait and doze modes, the chip select module continues operation but does not generate
interrupts; therefore it cannot bring a device out of a low-power mode. This module is stopped in
stop mode.
8.3.2.6
In wait and doze modes, the DMA controller is capable of bringing the device out of a low-power
mode by generating an interrupt either upon completion of a transfer or upon an error condition.
The completion of transfer interrupt is generated when DMA interrupts are enabled by the setting
of the DCR[INT] bit, and an interrupt is generated when the DSR[DONE] bit is set. The interrupt
upon error condition is generated when the DCR[INT] bit is set, and an interrupt is generated when
either the CE, BES or BED bit in the DSR becomes set.
The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power
mode.
8.3.2.7
In wait and doze modes, the UART may generate an interrupt to exit the low-power modes.
In stop mode, the UARTs stop immediately and freeze their operation, register values, state
machines, and external pins. During this mode, the UART clocks are shut down. Coming out of
stop mode returns the UARTs to operation from the state prior to the low-power mode entry.
8.3.2.8
When the I
stop mode, the I
low-power mode. For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and
the setting of the I2SR[IIF] generates the interrupt signal to the CPU and interrupt controller. The
Freescale Semiconductor
• Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART
• The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode.
functions.
2
Chip Select Module
DMA Controller (DMA0–DMA3)
UART Modules (UART0, UART1, and UART2)
I
C Module is enabled by the setting of the I2CR[IEN] bit and when the device is not in
2
C Module
The SDRAM is inaccessible while in the self-refresh mode.
Therefore, if stop mode is used the vector table and any interrupt
handlers that could wake the processor should not be stored in or
attempt to access SDRAM.
2
C module is operable and may generate an interrupt to bring the device out of a
MCF5271 Reference Manual, Rev. 2
NOTE
Functional Description
8-7