MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 569

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

30.5.2.2 Transmit Packet Format
The basic transmit packet,
30.5.3 BDM Command Set
Table 30-18
descriptions of each command. Issuing a BDM command when the processor is accessing debug
module registers using the WDEBUG instruction causes undefined behavior.
Freescale Semiconductor
15–0
15–0
Bits
Bits
16
16
—
16
summarizes the BDM command set. Subsequent paragraphs contain detailed
15
Name
Name
—
D
D
S
14
Table 30-17. Transmit BDM Packet Field Description
Table 30-16. Receive BDM Packet Field Description
13
Status. Indicates the status of CPU-generated messages listed below. The not-ready
response can be ignored unless a memory-referencing cycle is in progress. Otherwise,
the debug module can accept a new serial transfer after 32 processor clock periods.
Data. Contains the message to be sent from the debug module to the development
system. The response message is always a single word, with the data field encoded as
shown above.
Reserved, should be cleared.
Data bits 15–0. Contains the data to be sent from the development system to the debug
module.
Figure
12
Figure 30-14. Transmit BDM Packet
11
30-14, consists of 16 data bits and 1 reserved bit.
MCF5271 Reference Manual, Rev. 2
S
0
0
1
1
1
10
9
FFFF
FFFF
0000
0001
Data
xxxx
8
D
7
Description
Description
Error–Terminated bus cycle; data invalid
Not ready with response; come again
6
Valid data transfer
5
Illegal Command
Status OK
Message
4
3
Background Debug Mode (BDM)
2
1
0
30-19