MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 556

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
These registers are accessed through the BDM port by the commands,
described in
field, DRc, that specifies the register, as shown in
30-6
0x0A–0x0B Reserved
0x01–0x05 Reserved
DRc[4–0]
0x0C
0x0D
0x0E
0x00
0x06
0x07
0x08
0x09
0x0F
Section 30.5.3.3, “Command Set
Note: Each debug register is accessed as a 32-bit register; reserved fields above are not
used (don’t care). All debug control registers are writable from the external development
system or the CPU via the WDEBUG instruction. CSR is write-only from the programming
model. It can be read or written through the BDM port using the rdmreg and wdmreg
commands.
[31:24]
Configuration/status register
Address attribute trigger register
Trigger definition register
Program counter breakpoint register
Program counter breakpoint mask register
Address breakpoint high register
Address breakpoint low register
Data breakpoint register
Data breakpoint mask register
—
Figure 30-4. Debug Programming Model
Table 30-3. Debug Programming Model
Table 30-4. BDM/Breakpoint Registers
Address High Breakpoint Register
Address Low Breakpoint Register
Data Breakpoint Mask Register
Register Name
Configuration/Status Register
PC Breakpoint Mask Register
Trigger Definition Registers
[23:16]
Data Breakpoint Register
PC Breakpoint Register
MCF5271 Reference Manual, Rev. 2
Address Attribute Trigger Register
[15:8]
Descriptions.” These commands contain a 5-bit
Table
30-4.
Mnemonic
DBMR
PBMR
ABHR
AATR
ABLR
CSR
TDR
PBR
DBR
—
—
[7:0]
0x0001_0000
0x0000_0005
0x0000_0000
Initial State
Mnemonic
—
—
—
—
—
—
—
—
WDMREG
DBMR
PBMR
ABHR
ABLR
AATR
CSR
DBR
PBR
TDR
Freescale Semiconductor
p. 30-14
p. 30-13
p. 30-13
p. 30-12
p. 30-12
p. 30-9
p. 30-7
p. 30-8
p. 30-8
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and
—
—
RDMREG
,