MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 404

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Programmable Interrupt Timer Modules (PIT0–PIT3)
21-4
15–12
11–8
Bits
7
6
5
4
3
2
Name
DOZE
OVW
DBG
PRE
PIE
PIF
—
—
Reserved, should be cleared.
Prescaler. The read/write prescaler bits select the system clock divisor to generate the PIT
clock. To accurately predict the timing of the next count, change the PRE[3:0] bits only
when the enable bit (EN) is clear. Changing PRE[3:0] resets the prescaler counter. System
reset and the loading of a new value into the counter also reset the prescaler counter.
Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing
the EN bit stops the prescaler counter.
Reserved, should be cleared.
Doze mode bit. The read/write DOZE bit controls the function of the PIT in doze mode.
Reset clears DOZE.
0 PIT function not affected in doze mode
1 PIT function stopped in doze mode
When doze mode is exited, timer operation continues from the state it was in before
entering doze mode.
Debug mode bit. Controls the function of the PIT in debug mode. Reset clears DBG. During
debug mode, register read and write accesses function normally. When debug mode is
exited, timer operation continues from the state it was in before entering debug mode, but
any updates made in debug mode remain.
0 PIT function not affected in debug mode
1 PIT function stopped in debug mode
Note: Changing the DBG bit from 1 to 0 during debug mode starts the PIT timer. Likewise,
Overwrite. Enables writing to PMRn to immediately overwrite the value in the PIT counter.
0 Value in PMRn replaces value in PIT counter when count reaches 0x0000.
1 Writing PMRn immediately replaces value in PIT counter.
PIT interrupt enable. This read/write bit enables the PIF flag to generate interrupt requests.
0 PIF interrupt requests disabled
1 PIF interrupt requests enabled
PIT interrupt flag. This read/write bit is set when the PIT counter reaches 0x0000. Clear
PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF.
0 PIT count has not reached 0x0000.
1 PIT count has reached 0x0000.
changing the DBG bit from 0 to 1 during debug mode stops the PIT timer.
Table 21-3. PCSRn Field Descriptions
MCF5271 Reference Manual, Rev. 2
0000
0001
0010
1101
1110
PRE
1111
...
Description
System Clock Divisor
2
2
2
2
2
2
...
13
14
15
0
1
2
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