MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 48

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Overview
and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and
further decoding is available for protection from read-only access.
1.3.18 SDRAM Controller
The SDRAM controller provides all required signals for glueless interfacing to a variety of
JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software configurable
for different page sizes. To maintain refresh capability without conflicting with concurrent
accesses on the address and data buses, SD_SRAS, SD_SCAS, SD_WE, SD_CS[1:0] and
SD_CKE are dedicated SDRAM signals.
1.3.19 Reset
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals
to the system, and keep track of what caused the last reset. The power management registers for
the internal low-voltage detect (LVD) circuit are implemented in the reset module. There are six
sources of reset:
External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are
also software-readable status flags indicating the cause of the last reset.
1.3.20 GPIO
Like the MC68332, unused bus interface and peripheral pins on the MCF5271 can be used as
discrete general-purpose inputs and outputs. These are managed by a dedicated GPIO module that
logically groups all pins into ports located within a contiguous block of memory-mapped control
registers.
All of the pins associated with the external bus interface may be used for several different
functions. Their primary function is to provide an external memory interface to access off-chip
resources. When not used for this, all of the pins may be used as general-purpose digital I/O pins.
In some cases, the pin function is set by the operating mode, and the alternate pin functions are not
supported.
The digital I/O pins on the MCF5271 are grouped into 8-bit ports. Some ports do not use all eight
bits. Each port has registers that configure, monitor, and control the port pins.
1-12
• External
• Power-on reset (POR)
• Watchdog timer
• Phase locked-loop (PLL) loss of lock
• PLL loss of clock
• Software
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor