MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 336

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Synchronous DRAM Controller Module
18.3.5 Initialization Sequence
Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller supports
this sequence with the following procedure:
18-18
(DCR[COC] = 0)
1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before
2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet enable
3. Issue a
4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur.
5. Before issuing the
6. Issue the
SD_CS[0] or [1]
any action is taken on the SDRAMs. This is normally around 100 µs.
PALL
location. Wait the time (determined by t
allow the
SDRAM. Note that mode register settings are driven on the SDRAM address bus, so care
must be taken to change DMR[BAM] if the mode register configuration does not fall in
the address range determined by the address mask bits. After the mode register is set,
DMR mask bits can be restored to their desired configuration.
SD_SRAS
SD_SCAS
CLKOUT
SD_CKE
SD_WE
or
PALL
REF
MRS
MRS
commands.
command to the SDRAMs by setting DACR[IP] and accessing a SDRAM
PALL
command by setting DACR[IMRS] and accessing a location in the
to execute properly
t
RCD
MRS
= 2
Figure 18-9. Self-Refresh Operation
command, determine if the DMR mask bits need to be modified to
SELF
MCF5271 Reference Manual, Rev. 2
Refresh
Active
Self-
SELFX
RP
) before any other execution.
t
RC
= 6
Freescale Semiconductor
Possible
ACTV
First