MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 357

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
19.2.4.5 Ethernet Control Register (ECR)
ECR is a read/write user register, though both fields in this register may be altered by hardware as
well. The ECR is used to enable/disable the FEC.
Freescale Semiconductor
Address
Address
Reset
Reset
Reset
Reset
31–25
23–0
31–2
Bits
Bits
W
W
R
R
24
W
W
R
R
31
15
0
1
0
0
31
15
0
0
0
0
30
14
0
1
0
0
Name
TDAR
Name
30
14
0
0
0
0
Figure 19-5. Transmit Descriptor Active Register (TDAR)
29
13
0
1
0
0
29
13
0
0
0
0
Figure 19-6. Ethernet Control Register (ECR)
Reserved, should be cleared.
Set to one when this register is written, regardless of the value written. Cleared by the FEC
device whenever no additional “ready” descriptors remain in the transmit ring. Also cleared
when ECR[ETHER_EN] is cleared.
Reserved, should be cleared.
Reserved.
28
12
0
1
0
0
28
12
0
0
0
0
Table 19-7. TDAR Field Descriptions
Table 19-8. ECR Field Descriptions
27
11
0
0
0
0
27
11
0
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
0
0
0
0
26
10
0
0
0
0
25
0
0
0
0
9
25
0
0
0
0
9
IPSBAR + 0x1014
IPSBAR + 0x1024
TDAR
24
0
0
0
0
8
24
0
0
0
8
23
0
0
0
0
7
Description
Description
23
0
0
7
0
0
22
0
0
0
0
6
22
0
0
0
0
6
21
0
0
0
0
5
21
0
0
0
0
5
20
0
0
0
0
4
20
0
0
0
0
4
19
Memory Map/Register Definition
0
0
0
0
3
19
0
0
0
0
3
18
0
0
0
2
0
18
0
0
0
0
2
ETHER
_EN
17
0
0
0
1
17
0
0
0
0
1
RESET
16
0
0
0
0
0
16
0
0
0
0
19-13

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