MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 282

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DMA Controller Module
Figure 14-10
not parked on the bus, so the diagram shows how the CPU can generate multiple bus cycles during
DMA transfers. In cycle-steal mode, the maximum length of DREQ assertion to maintain a single
transfer is configuration-dependent. To avoid multiple transfers, for single-address accesses, no
hold signal, byte accesses, and idle channels, DREQ may be asserted for no more than four clock
cycles.
Figure 14-11
memory.
14-18
Figure 14-10. Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer
SD_SRAS
SD_SCAS
DRAMW
RAS[1:0]
CAS[3:0]
SIZ[1:0]
DACKn
A[31:0]
D[31:0]
DREQn
CLKIN
R/W
CSx
TIP
AS
TA
TS
shows a single-address DMA transfer in which an external peripheral is reading from
shows a dual-address, external peripheral-to-SDRAM DMA transfer. The DMA is
CPU
MCF5271 Reference Manual, Rev. 2
DMA Read
CPU
DMA Write
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CPU