MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 616

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Collision handling 19-46
Core
D
Debug
Index-2
system clock 7-15
block diagram 3-1
low-power modes 8-6
pipelines 3-1
registers
BDM
low-power modes 8-10
memory map 30-5
real-time support 30-37
registers
signals
CLKOUT 7-7
EXTAL 7-7
RSTOUT 7-7
XTAL 7-7
address (An) 3-3
condition code (CCR) 3-4
data (Dn) 3-2
program counter (PC) 3-3
stack pointer (A7) 3-3
status register (SR) 3-6
vector base (VBR) 3-7
commands
CPU halt 30-16
receive packet 30-18
recommended pinout 30-45
serial interface 30-17
transmit packet 30-19
address attribute trigger (AATR) 30-7
address breakpoint (ABLR, ABHR) 30-8
configuration/status (CSR) 30-9
data breakpoint/mask (DBR, DBMR) 30-12
program counter breakpoint/mask (PBR,
trigger definition (TDR) 30-14
DUMP 30-27
FILL 30-29
format 30-21
GO 30-31
NOP 30-31
RAREG/RDREG 30-23
RCREG 30-32
RDMREG 30-35
READ 30-25
summary 30-19
WAREG/WDREG 30-24
WCREG 30-34
WDMREG 30-36
WRITE 30-26
PBMR) 30-13
–
,
30-40
3-7
MCF5271 Reference Manual, Rev. 2
DMA
DMA controller
E
EMAC
EPORT
taken branch 30-4
trace 30-2
data transfer
channel prioritization 14-15
data transfer 14-4
low-power modes 8-7
programming 14-15
registers
data representation 4-14
instructions
MAC, comparison 4-1
memory map 4-6
opcodes 4-14
operation
registers
low-power modes 8-10
memory map 15-2
registers
breakpoint (BKPT) 30-2
debug data (DDATA3–0) 30-2
development serial clock (DSCLK) 30-2
development serial input (DSI) 30-2
development serial output (DSO) 30-2
processor status (PST3–0) 30-2
PSTCLK 30-2
requests 14-16
auto alignment 14-19
bandwidth control 14-20
requests 14-14
termination 14-20
byte count (BCRn) 14-8
control (DCRn) 14-10
destination address (DARn) 14-8
request control (DMAREQC) 14-6
source address (SARn) 14-7
status (DSRn) 14-9
execution timing 3-25
summary 4-12
fractional 4-9
general 4-3
mask (MASK) 4-11
status (MACSR) 4-6
data direction (EPDDR) 15-4
flag (EPFR) 15-6
pin assignment (EPPAR) 15-3
pin data (EPPDR) 15-6
port data (EPDR) 15-5
port interrupt enable (EPIER) 15-5
,
,
15-1
4-13
Freescale Semiconductor