MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 361

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.2.4.8 MIB Control Register (MIBC)
The MIBC is a read/write register used to provide control of and to observe the state of the MIB
block. This register is accessed by user software if there is a need to disable the MIB block
operation. For example, in order to clear all MIB counters in RAM the user should disable the MIB
block, then clear all the MIB RAM locations, then enable the MIB block. The MIB_DIS bit is reset
to 1. See
Freescale Semiconductor
Address
Reset
Reset
29–0
Bits
31
30
W
W
R MIB_
R
Table 19-3
DIS
31
15
1
0
0
System Clock Frequency
MIB_IDLE
MIB_DIS
MIB_
IDLE
Name
30
14
1
0
0
—
for the locations of the MIB counters.
25 MHz
33 MHz
40 MHz
50 MHz
66 MHz
75 MHz
29
13
Table 19-11. Programming Examples for MSCR
0
0
0
0
A read/write control bit. If set, the MIB logic will halt and not update any MIB counters.
A read-only status bit. If set the MIB block is not currently updating any MIB counters.
Reserved.
Figure 19-9. MIB Control Register (MIBC)
28
12
0
0
0
0
Table 19-12. MIBC Field Descriptions
27
11
0
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
0
0
0
0
MSCR[MII_SPEED]
25
0
0
0
0
9
IPSBAR + 0x1064
0x5
0x8
0xA
0xE
0xF
0x7
24
0
0
0
0
8
23
Description
0
0
0
0
7
22
0
0
6
0
0
21
0
0
0
0
EMDC frequency
5
2.36 MHz
2.36 MHz
2.5 MHz
2.5 MHz
2.5 MHz
2.5 MHz
20
0
0
0
0
4
Memory Map/Register Definition
19
0
0
0
0
3
18
0
0
0
0
2
17
0
0
0
0
1
16
0
0
0
0
0
19-17