MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 370
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Fast Ethernet Controller (FEC)
19.2.4.20 FIFO Receive Start Register (FRSR)
The FRSR is programmed by the user to indicate the starting address of the receive FIFO. FRSR
marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses
from the start of the FIFO to the location four bytes before the address programmed into the FRSR.
The receive FIFO uses addresses from FRSR to FRBR inclusive.
The FRSR register is initialized by hardware at reset. FRSR only needs to be written to change the
default value.
19.2.4.21 Receive Descriptor Ring Start Register (ERDSR)
The ERDSR is written by the user. It provides a pointer to the start of the circular receive buffer
descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is
recommended it be made 128-bit aligned (evenly divisible by 16).
19-26
Address
Reset
Reset
31–10
31–10
Bits
Bits
9–2
1–0
9–2
1–0
W
W
R
R
31
15
0
0
0
0
R_FSTART Address of first receive FIFO location. Acts as delimiter between receive and transmit
R_BOUND Read-only. Highest valid FIFO RAM address.
Name
Name
30
14
0
0
0
0
—
—
—
—
Figure 19-21. FIFO Receive Start Register (FRSR)
29
13
0
0
0
0
Reserved, read as 0 (except bit 10, which is read as 1).
Reserved, should be cleared.
Reserved, read as 0 (except bit 10, which is read as 1).
FIFOs.
Reserved, read as 0.
28
12
Table 19-23. FRBR Field Descriptions
0
0
0
0
Table 19-24. FRSR Field Descriptions
27
11
0
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
0
0
0
1
25
0
0
0
9
IPSBAR + 0x1150
24
0
0
1
8
Descriptions
Descriptions
23
0
0
0
7
R_FSTART
22
0
0
6
0
21
0
0
0
5
20
0
0
0
4
19
0
0
0
3
Freescale Semiconductor
18
0
0
0
2
17
0
0
0
0
1
16
0
0
0
0
0
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