MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 405
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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21.2.1.2 PIT Modulus Register (PMRn)
The 16-bit read/write PMRn contains the timer modulus value that is loaded into the PIT counter
when the count reaches 0x0000 and the PCSRn[RLD] bit is set.
When the PCSRn[OVW] bit is set, PMRn is transparent, and the value written to PMRn is
immediately loaded into the PIT counter. The prescaler counter is reset anytime a new value is
loaded into the PIT counter and also during reset. Reading the PMRn returns the value written in
the modulus latch. Reset initializes PMRn to 0xFFFF.
21.2.1.3 PIT Count Register (PCNTRn)
The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two
8-bit reads is not guaranteed to be coherent. Writing to PCNTRn has no effect, and write cycles
are terminated normally.
Freescale Semiconductor
Address
Address
Reset
Reset
Bits
1
0
W
W
R
R
15
15
1
1
Name
RLD
14
14
EN
1
1
Table 21-3. PCSRn Field Descriptions (Continued)
13
13
1
1
Reload bit. The read/write reload bit enables loading the value of PMRn into the PIT
counter when the count reaches 0x0000.
0 Counter rolls over to 0xFFFF on count of 0x0000
1 Counter reloaded from PMRn on count of 0x0000
PIT enable bit. Enables PIT operation. When the PIT is disabled, the counter and prescaler
are held in a stopped state. This bit is read anytime, write anytime.
0 PIT disabled
1 PIT enabled
Figure 21-3. PIT Modulus Register (PMRn)
Figure 21-4. PIT Count Register (PCNTR)
IPSBAR + 0x0015_0004 (PIT0), IPSBAR + 0x0016_0004 (PIT1),
IPSBAR + 0x0015_0002 (PIT0);IPSBAR + 0x0016_0002 (PIT1);
IPSBAR + 0x0017_0002 (PIT2); IPSBAR + 0x0018_0002 (PIT3)
IPSBAR + 0x0017_0004 (PIT2), IPSBAR + 0x0018_0004 (PIT3)
12
12
1
1
11
11
1
1
MCF5271 Reference Manual, Rev. 2
10
10
1
1
1
1
9
9
1
1
8
8
PM
PC
Description
1
1
7
7
6
1
6
1
1
1
5
5
1
1
4
4
Memory Map/Register Definition
1
1
3
3
1
1
2
2
1
1
1
1
1
1
0
0
21-5
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