MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 127

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Address
Reset
Reset
31–24
23–16
14–13
12–7
Bits
15
W
W EN
6
R
R
31
15
0
0
IPSBAR space cannot be cached. Ensure that ACR[AB] does not fall
within this space.
Name
30
14
0
0
AM
SM
CM
EN
AB
—
SM
Figure 5-3. Access Control Registers (ACR0, ACR1)
29
13
0
0
Address base. This 8-bit field is compared to address bits [31:24] from the processor's local
bus under control of the ACR address mask. If the address matches, the attributes for the
memory reference are sourced from the given ACR.
Address mask. This 8-bit field can mask any bit of the AB field comparison. If a bit in the
AM field is set, then the corresponding bit of the address field comparison is ignored.
ACR Enable. The EN bit defines the ACR enable. Hardware reset clears this bit, disabling
the ACR.
0 ACR disabled
1 ACR enabled
Supervisor mode. This two-bit field allows the given ACR to be applied to references based
on operating privilege mode of the ColdFire processor. The field uses the ACR for user
references only, supervisor references only, or all accesses.
00 Match if user mode
01 Match if supervisor mode
1x Match always—ignore user/supervisor mode
Reserved, should be cleared.
Cache mode. This bit defines the cache mode: 0 is cacheable, 1 is noncacheable.
0 Caching enabled
1 Caching disabled
28
12
0
0
AB
Table 5-7. ACR Field Descriptions
27
11
0
0
MCF5271 Reference Manual, Rev. 2
MOVEC with 0x004, MOVEC with 0x005
26
10
0
0
—
25
0
9
0
NOTE
24
0
0
8
23
0
7
0
Description
CM
22
0
0
6
BWE
21
0
0
5
20
0
0
4
AM
—
Memory Map/Register Definition
19
0
3
0
WP
18
0
0
2
17
0
0
1
—
16
0
0
0
5-11