MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 228

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

General Purpose I/O Module
12.3.1.2 Port Data Direction Registers (PDDR_x)
The PDDRs control the direction of the port x pin drivers when the pins are configured for general
purpose I/O. The PDDR_x registers are each eight bits wide, but not all ports use all eight bits. The
register definitions for all ports are shown in
The PDDRs are read/write. At reset, all bits in the PDDRs are cleared. Setting any bit in a PDDR_x
register configures the corresponding port x pin as an output. Clearing any bit in a PDDR_x
register configures the corresponding pin as an input.
12-12
Figure 12-6. Port SDRAM Output Data Register (PODR_SDRAM)
Figure 12-7. Port UARTH Output Data Register (PODR_UARTH)
Figure 12-8. Port QSPI Output Data Register (PODR_QSPI)
Address
Address
Address
Note: See above figures for bit field positions.
Reset
Reset
Reset
PODR_x
W
W
W
Name
R
R
R
—
0
0
0
0
0
0
Table 12-4. PODR_x Field Descriptions
7
7
7
Reserved, should be cleared.
Port x output data bits.
0 Drives 0 when the port x pin is general purpose output
1 Drives 1 when the port x pin is general purpose output
MCF5271 Reference Manual, Rev. 2
0
0
0
0
0
0
6
6
6
IPSBAR + 0x10_0006 (PODR_SDRAM)
IPSBAR + 0x10_0008 (PODR_UARTH)
IPSBAR + 0x10_000A (PODR_QSPI)
1
0
0
0
0
5
5
5
Figure 12-9
1
0
0
1
4
4
4
Description
PODR_SDRAM
1
0
0
1
3
3
3
through
PODR_QSPI
2
1
2
0
0
2
1
Figure
PODR_UARTH
1
1
1
1
1
1
12-15.
1
1
1
0
0
0
Freescale Semiconductor