MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 591
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Instruction
bcc.{b,w}
bra.{b,w}
bsr.{b,w}
byterev.l
bitrev.l
divu.w
addq.l
addx.l
divs.w
cmpi.l
addi.l
andi.l
cmp.l
divs.l
divu.l
add.l
add.l
and.l
and.l
bchg
bchg
bset
bset
clr.w
asl.l
asr.l
clr.b
bclr
bclr
btst
btst
clr.l
Table 30-23. PST/DDATA Specification for User-Mode Instructions
Operand Syntax
{Dy,#imm},Dx
{Dy,#imm},Dx
#imm,<ea>x
#imm,<ea>x
#imm,<ea>x
#imm,<ea>x
#imm,<ea>x
<ea>y,Rx
Dy,<ea>x
<ea>y,Dx
Dy,<ea>x
Dy,<ea>x
Dy,<ea>x
Dy,<ea>x
Dy,<ea>x
<ea>y,Rx
<ea>y,Dx
<ea>y,Dx
<ea>y,Dx
<ea>y,Dx
#imm,Dx
#imm,Dx
#imm,Dx
<ea>x
<ea>x
<ea>x
Dy,Dx
Dx
Dx
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
if taken, then PST = 0x5, else PST = 0x1
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x5
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}
PST = 0x5, {PST = 0xB, DD = destination operand}
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0x8, DD = destination operand}
PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x1, {PST = 0x9, DD = destination operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
MCF5271 Reference Manual, Rev. 2
PST/DDATA
Processor Status, DDATA Definition
30-41
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