MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 552

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
30.2
Table 30-1
related to a rising edge of the processor’s clock signal. The standard 26-pin debug connector is
shown in
Figure 30-2
30.3
Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The
ColdFire solution is to include a parallel output port providing encoded processor status and data
to an external development system. This port is partitioned into two 4-bit nibbles: one nibble
allows the processor to transmit processor status, (PST), and the other allows operand data to be
30-2
Development Serial
Clock (DSCLK)
Development Serial
Input (DSI)
Development Serial
Output (DSO)
Breakpoint (BKPT)
PSTCLK
Debug Data
(DDATA[3:0])
Processor Status
(PST[3:0])
Signal
Section 30.8, “Freescale-Recommended BDM
External Signal Description
Real-Time Trace Support
describes debug module signals. All ColdFire debug signals are unidirectional and
PST
shows PSTCLK timing with respect to PST and DDATA.
or
PSTCLK
DDATA
Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on
two consecutive rising PSTCLK edges.) Clocks the serial communication port to the debug
module during packet transfers. Maximum frequency is 1/5 the processor status clock (PSTCLK)
speed. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO
changes state.
Internally synchronized input that provides data input for the serial communication port to the
debug module.
Provides serial output communication for debug module responses. DSO is registered internally.
Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted
state after the current instruction completes. Halt status is reflected on processor status signals
(PST[3:0]) as the value 0xF.
See
DDATA values.
These output signals display the register breakpoint status as a default, or optionally, captured
address and operand values. The capturing of data values is controlled by the setting of the
CSR. Additionally, execution of the WDDATA instruction by the processor captures operands
which are displayed on DDATA. These signals are updated each processor cycle.
These output signals report the processor status.
signals. These outputs indicate the current status of the processor pipeline and, as a result, are
not related to the current bus transfer. The PST value is updated each processor cycle.
Figure
30-2. PSTCLK indicates when the development system should sample PST and
Table 30-1. Debug Module Signals
Figure 30-2. PSTCLKTiming
MCF5271 Reference Manual, Rev. 2
Description
Pinout.”
Table 30-2
shows the encoding of these
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