MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 615

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

B
BDM, see Debug
Bus
C
Cache
CCM
Freescale Semiconductor
arbitration 11-9
characteristics 17-2
data transfer
operands, misaligned 17-16
SACU 11-12
block diagram 5-3
coherency 5-4
fill buffer 5-2
invalidation 5-4
miss fetch algorithm 5-5
organization 5-1
registers
SRAM interaction 5-3
configuration
memory map 9-3
operation
registers
fixed mode 11-11
round-robin mode 11-10
back-to-back cycles 17-10
burst cycles 17-11
cycle execution 17-4
cycle states 17-5
fast termination cycle 17-9
read cycle 17-7
write cycle 17-8
access control 0–1 (ACRn) 3-8
control (CACR) 3-7
boot device 9-10
chip mode 9-9
chip select 9-11
clock mode 9-10
output pad strength 9-10
reset 9-7
low-power modes 8-9
chip configuration (CCR) 9-4
line read bus cycles 17-12
line transfers 17-12
line write bus cycles 17-14
,
5-5
–
11-12
,
5-7
,
5-10
MCF5271 Reference Manual, Rev. 2
Index
Chip select module
Clock module
signals
byte strobes (BS3–0) 16-2
code example 16-11
memory map 16-6
operation
registers
signals
memory map 7-8
operation
PLL
registers
signals
chip identification (CIR) 9-7
reset configuration (RCON) 9-5
CLKMOD1–0 9-2
RCON 9-2
general 16-3
low-power modes 8-7
port sizing 16-4
wait state 16-4
address (CSARn) 16-7
control (CSCRn) 16-9
mask (CSMRn) 16-8
chip select (CS7–0) 16-1
output enable (OE) 16-1
low-power modes 7-6
normal PLL mode 7-5
reset 7-14
charge pump/loop filter 7-22
lock detection 7-23
loss-of-clock
loss-of-lock
multiplication factor divider (MFD) 7-23
operation 7-21
phase and frequency detector (PFD) 7-22
voltage control output (VCO) 7-23
synthesizer control (SYNCR) 7-8
synthesizer status (SYNSR) 7-11
CLKMOD1–0 7-7
alternate clock selection 7-25
detection 7-25
reset 7-25
stop mode 7-26
conditions 7-24
reset 7-25
,
8-10
,
7-23
Index-1