MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 378

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.3
This section describes the operation of the FEC, beginning with the hardware and software
initialization sequence, then the software (Ethernet driver) interface for transmitting and receiving
frames.
Following the software initialization and operation sections are sections providing a detailed
description of the functions of the FEC.
19.3.1 Initialization Sequence
This section describes which registers are reset due to hardware reset, which are reset by the FEC
RISC, and what locations the user must initialize prior to enabling the FEC.
19.3.1.1 Hardware Controlled Initialization
In the FEC, registers and control logic that generate interrupts are reset by hardware. A hardware
reset deasserts output signals and resets general configuration bits.
Other registers reset when the ECR[ETHER_EN] bit is cleared. ECR[ETHER_EN] is deasserted
by a hard reset or may be deasserted by software to halt operation. By deasserting
ECR[ETHER_EN], the configuration control registers such as the TCR and RCR will not be reset,
but the entire data path will be reset.
19-34
1
Offset + 2
Offset + 4
Offset + 6
The transmit buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible
by 4. The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
Word
Functional Description
Table 19-29. Transmit Buffer Descriptor Field Definitions (Continued)
Once the software driver has set up the buffers for a frame, it should
set up the corresponding BDs. The last step in setting up the BDs for
a transmit frame should be to set the R bit in the first BD for the frame.
The driver should follow that with a write to TDAR which will trigger
the FEC to poll the next BD in the ring.
15–0
15–0
15–0
Bits
Field Name
A[31:16]
A[15:0]
Length
Data
MCF5271 Reference Manual, Rev. 2
Data Length, written by user.
Data length is the number of octets the FEC should transmit from this BD’s
data buffer. It is never modified by the FEC. Bits [15:5] are used by the DMA
engine, bits[4:0] are ignored.
Tx data buffer pointer, bits [31:16]
Tx data buffer pointer, bits [15:0].
NOTE
Description
1
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