MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 15

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

16.1.1
16.2
16.2.1
16.2.2
16.2.3
16.3
16.3.1
16.3.1.1
16.3.2
16.3.2.1
16.4
16.4.1
16.4.1.1
16.4.1.2
16.4.1.3
16.5
17.1
17.1.1
17.2
17.3
17.4
17.5
17.5.1
17.5.2
17.5.3
17.5.4
17.5.5
17.5.6
17.5.7
17.5.7.1
17.5.7.2
17.5.7.3
17.6
17.7
Freescale Semiconductor
Paragraph
Number
External Signal Description .......................................................................................... 16-1
Chip Select Operation ................................................................................................... 16-3
Memory Map/Register Definition ................................................................................ 16-6
Code Example............................................................................................................. 16-11
Introduction................................................................................................................... 17-1
Bus and Control Signals ............................................................................................... 17-1
Bus Characteristics ....................................................................................................... 17-2
Bus Errors ..................................................................................................................... 17-3
Data Transfer Operation ............................................................................................... 17-3
Secondary Wait State Operation................................................................................. 17-15
Misaligned Operands .................................................................................................. 17-16
Overview................................................................................................................... 16-1
Chip Selects (CS[7:0]) .............................................................................................. 16-1
Output Enable (OE) .................................................................................................. 16-1
Byte Strobes (BS[3:0]).............................................................................................. 16-2
General Chip Select Operation ................................................................................. 16-3
Enhanced Wait State Operation................................................................................ 16-4
Chip Select Module Registers................................................................................... 16-7
Features..................................................................................................................... 17-1
Bus Cycle Execution................................................................................................. 17-4
Data Transfer Cycle States ....................................................................................... 17-5
Read Cycle................................................................................................................ 17-7
Write Cycle ............................................................................................................... 17-8
Fast Termination Cycles ........................................................................................... 17-9
Back-to-Back Bus Cycles ....................................................................................... 17-10
Burst Cycles............................................................................................................ 17-11
8-, 16-, and 32-Bit Port Sizing.............................................................................. 16-4
External Boot Chip Select Operation ................................................................... 16-6
Chip Select Address Registers (CSAR0–CSAR7) ............................................... 16-7
Chip Select Mask Registers (CSMR0–CSMR7) .................................................. 16-8
Chip Select Control Registers (CSCR0–CSCR7)................................................. 16-9
Line Transfers..................................................................................................... 17-12
Line Read Bus Cycles......................................................................................... 17-12
Line Write Bus Cycles........................................................................................ 17-14
External Interface Module (EIM)
MCF5271 Reference Manual, Rev. 2
Contents
Chapter 17
Title
Number
Page
xv