MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 200

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

System Control Module (SCM)
11.2 Memory Map/Register Definition
The memory map for the SCM registers is shown in
memory-mapped as offsets within the 1-Gbyte IPS address space and accesses are controlled to
these registers by the control definitions programmed into the SACU.
11-2
• IPS base address register (IPSBAR)
• Processor-local memory base address register (RAMBAR)
• System control registers
• System bus master arbitration programming model (MPARK)
• System access control unit (SACU) programming model
— Base address location for 1-Gbyte peripheral space
— User control bits
— Core reset status register (CRSR) indicates type of last reset
— Core watchdog control register (CWCR) for watchdog timer control
— Core watchdog service register (CWSR) to service watchdog timer
— Master privilege register (MPR)
— Peripheral access control registers (PACRs)
— Grouped peripheral access control register (GPACR)
0x00_000C
0x00_001C
0x00_002C
0x00_0000
0x00_0004
0x00_0008
0x00_0010
0x00_0014
0x00_0018
0x00_0020
0x00_0024
0x00_0028
IPSBAR
Offset
[31:24]
PACR0
PACR4
PACR7
CRSR
MPR
Table 11-1. SCM Register Map
MCF5271 Reference Manual, Rev. 2
[23:16]
PACR1
CWCR
—
—
DMAREQC
RAMBAR
IPSBAR
MPARK
—
—
—
Table
2
LPICR
PACR2
PACR5
PACR8
[15:8]
11-1. All the registers in the SCM are
—
1
PACR3
PACR6
CWSR
[7:0]
—
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