MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 193

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Functional Description
To protect data integrity, a synchronous reset source is not acted upon by the reset control logic
until the end of the current bus cycle. Reset is then asserted on the next rising edge of the system
clock after the cycle is terminated. Whenever the reset control logic must synchronize reset to the
end of the bus cycle, the internal bus monitor is automatically enabled regardless of the BME bit
state in the chip configuration register (CCR). Then, if the current bus cycle is not terminated
normally the bus monitor terminates the cycle based on the length of time programmed in the BMT
field of the CCR.
Internal byte, word, or longword writes are guaranteed to complete without data corruption when
a synchronous reset occurs. External writes, including longword writes to 16-bit ports, are also
guaranteed to complete.
Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control
logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the
system.
10.4.1.1 Power-On Reset
At power up, the reset controller asserts RSTOUT. RSTOUT continues to be asserted until V
DD
has reached a minimum acceptable level and, if PLL clock mode is selected, until the PLL
achieves phase lock. Then after approximately another 512 cycles, RSTOUT is negated and the
part begins operation.
10.4.1.2 External Reset
Asserting the external RESET for at least four rising CLKOUT edges causes the external reset
request to be recognized and latched. The bus monitor is enabled and the current bus cycle is
completed. The reset controller asserts RSTOUT for approximately 512 cycles after RESET is
negated and the PLL has acquired lock. The part then exits reset and begins operation.
In low-power stop mode, the system clocks are stopped. Asserting the external RESET in stop
mode causes an external reset to be recognized.
10.4.1.3 Watchdog Timer Reset
A watchdog timer timeout causes timer reset request to be recognized and latched. The bus
monitor is enabled and the current bus cycle is completed. If the RESET is negated and the PLL
has acquired lock, the reset controller asserts RSTOUT for approximately 512 cycles. Then the
part exits reset and begins operation.
10.4.1.4 Loss-of-Clock Reset
This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set and
either the PLL reference or the PLL itself fails. The reset controller asserts RSTOUT for
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
10-5